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esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 1/12 ultra high-psrr, low-noise, 300ma cmos linear regulator general description the emp8130 features ultra-high power supply rejection ratio, low output voltage noise, low dropout voltage, low quiescent current and fast transient response. it guar antees delivery of 300ma output current and supports preset output voltages ranging from 0.8v to 4.0v with 0.1v increment. based on its low quiescent current consumption and its less than 1ua shutdown mode of logical operation, the emp8130 is ideal for battery-powered applications. the high power supply rejection ratio of the emp8130 holds well for low input voltages typically encountered in battery-operated systems. the regulator is stable with small ceramic capacitive loads (1f typical). the emp8130 is available in miniature sot-23-5 package. applications g wireless handsets g pcmcia cards g dsp core power g hand-held instruments g battery-powered systems g portable information appliances features g 300ma guaranteed output current g 75db typical psrr at 1khz g 260mv (v out =3.3v) typical dropout at 300ma g 52a typical quiescent current g less than 1a typical shutdown mode g fast line and load transient response g 1.7v to 5.5v input range g auto-discharge during chip disable g 0.8v to 4.0v output voltage range g stable with small ceramic output capacitors g fold-back over current protection g 1% output voltage tolerance typical application in out v in v out emp8130 en gnd 1uf ceramic capacitor on/off 1uf ceramic capacitor
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 2/12 connection diagrams order information emp8130-xxvn05nrr -------------------------------------------------- xx output voltage -------------------------------------------------- vn05 sot-23-5 package -------------------------------------------------- nrr rohs & halogen free package rating: -40 to 85c package in tape & reel order, marking & packing information package vout-a product id. marking packing 0.8v emp8130-08vn05nrr 1.0v emp8130-10vn05nrr 1.2v emp8130-12vn05nrr 1.3v emp8130-13vn05nrr 1.5v emp8130-15vn05nrr 1.8v emp8130-18vn05nrr 2.5v emp8130-25vn05nrr 2.8v emp8130-28vn05nrr 3.0v EMP8130-30VN05NRR sot-23-5 3.3v emp8130-33vn05nrr tape & reel 3kpcs
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 3/12 pin functions name sot-23-5 function in 1 supply voltage input. require a minimum input capacitor of cl ose to 1f ceramic capacitor to ensure stability and sufficient decoupling from the ground pin. gnd 2 ground pin. en 3 enable input. enable the regulator by pulling the en pin high. to keep the regulator on during normal operation, connect the en pin to v in . the en pin must not exceed v in under all operating conditions. nc 4 no connected. out 5 regulated output voltage pin. a small 1f ceramic capacitor is needed from this pin to ground to assure stability. functional block diagram fig.1. functional block diagram of emp8130
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 4/12 absolute maximum ratings (notes 1, 2) in, en, out -0.3v to 6.5v power dissipation (note 8) storage temperature range -65c to 150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec.) 260c esd rating human body model 2kv machine model 200v operating ratings (note 1, 2) supply voltage 1.7v to 5.5v operating temperature range -40c to 85c thermal resistance ( ja , note 3)) 152c/w (sot-23-5) thermal resistance ( jc , note 4)) 81c/w (sot-23-5) electrical characteristics unless otherwise specified, all limits guaranteed for v in = v out +1v (note 5), v en =v in , c in = c out = 1f, t a = 25c. boldface limits apply for the operating temperature extremes: -40c and 85c. symbol parameter conditions min typ (note. 7) max units v in input voltage 1.7 5.5 v v out output voltage 0.8 4.0 v vout>2.0v, t=25 x0.99 x1.01 v vout<=2.0v, t=25 -20 +20 mv vout>2v, -40~85c x0.97 x1.03 v v otl output voltage tolerance vout<=2v, -40~85c -60 60 mv i out maximum output current average dc current rating 300 ma i sc short current limit 40 ma i q quiescent current i out = 0ma 52 75 a i sd shutdown supply current v out = 0v, en = gnd 0.2 1 a i out = 300ma, vout=0.8v 860 i out = 300ma, vout=1.2v 580 i out = 300ma, vout=1.5v 440 i out = 300ma, vout=1.8v 380 i out = 300ma, vout=2.8v 290 v do dropout voltage (note4) i out = 300ma, vout=3.3v 260 mv line regulation i out = 1ma, (v out + 1v) v in 5.5v 0.02 0.1 %/v v out load regulation 1ma i out 300ma 10 30 mv psrr power supply rejection ratio f = 1khz, ripple 0.2 vp-p, vin=set vout +1v, iout = 30ma 75 db e n output voltage noise v out =0.8v, i out =30ma, 10hz f 100khz 40 v rms 1.0 v en en input threshold 0.4 v i en en input bias current en=gnd or vin 0.1 1 a
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 5/12 note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications do not apply when operating the device outside of its rated operating conditions. note 2: all voltages are with respect to the potential at the ground pin. note 3: ja is measured in the natural convection at t a =25 on a high effective thermal conductivity test board (2 layers, 2s0p). note 4: jc represents the resistance to the heat flows the chip to package top case. note 5: dropout voltage is measured by reducing v in until v out drops 100mv from its nominal value at v in -v out = 1v. note 6: maximum power dissipation for the device is ca lculated using the following equations: ja a t - j(max) t d p = where t j (max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. e.g. for the sot-23-5 package ja = 152c/w, t j (max) = 150c and using t a = 25c, the maximum power dissipation is found to be 0.82w. the derating factor (-1/ ja ) = -6.6mw/c, thus below 25c the power dissipation fi gure can be increased by 6.6mw per degree, and similarity decreased by this factor for temperatures above 25c. note 7: typical values represent the most likely parametric norm.
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 6/12 typical performance characteristics unless otherwise specified, v in = v out (nom) + 1v, v en =v in , c in = c out = 1f, t a = 25c psrr vs. frequency (v out =0.8v) psrr vs. frequency (v out =3.3v) cround current vs. v in (v out =0.8v) ground current vs. i out (v out =0.8v) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 0.0v 1.0v 2.0v 3.0v 4.0v 5.0v 6.0v vin (v) ground current (ua) ? ?? ?? ? ?? ??? ??? ??? ?? ? ?? ?? ??? ?? ??? ??? ??? ??? ?? ??? 3??3??? output voltage noise output current limit (fold-back)
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 7/12 typical performance characteristics (cont.) unless otherwise specified, v in = v out (nom) + 1v, v en =v in , c in = c out = 1f, t a = 25c enable response (v out =0.8v) disable response (v out =0.8v) line transient (iout=30ma,vin=4.3v~5.3v,v out =3.3v) line transient (i out=300ma,vin=4.3v~5.3v,v out =3.3v) load transient (v out =0.8v, i out =50ma to 100ma) load transient (v out =0.8v, i out =1ma to 300ma)
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 8/12 application information general description referring to fig.1 as shown in the functional block diagram section, the emp8130 adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function. the sub vout-select form the feedback circuit which sa mples the output voltage for the error amplifier?s non-inverting input. the inverting input is set to the ba ndgap reference voltage. due to its high open-loop gain, the error amplifier ensures that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset voltage reference voltage. the error amplif ier compares the voltage difference at its inputs and produces an appropriate driving volt age to the p-channel mos pass transistor, which controls the amount of current reaching the output. if there are changes in the output voltage due to load changes, the feedback resistors register these changes to the non-inverting input of the error amplifie r. the error amplifier then adjusts its driving voltage to maintain virtual short between it s two input nodes under all loading conditions. the regulation of the output voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. this negative feedback control topology is fu rther augmented by the shut down, the temperature and current protection circuitry. output capacitor the emp8130 is specially designed for use with ceramic output capacitors of as low as 1 f to take advantage of the savings in cost and space, as well as the superior filtering of high frequency noise. capacitors of higher value or other types may be used, but it is important to make sure its equivalent series resistance (esr) be restricted to less than 0.5 ? . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors suitable for use with the emp8130 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. no-load stability the emp8130 is capable of stable operation during no-load conditions, a mandatory feature for some applications such as cmos ram keep-alive operations. input capacitor a minimum input capacitance of 1f is required for emp8130. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. a case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will esta blish a pseudo lcr network, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions.
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 9/12 power dissipation thermal overload results from excessive power dissipation that causes the ic junction temperature to increase beyond a safe operating level. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipate to its ambient air. an ic junction with a low thermal resistance is preferred because it is relati vely effective in dissipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and t j is as follows: t j = ja x (p d ) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out ) as the above equations show, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermally overloading the emp81 30, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to -output differential voltages can increase the ic die temperature significantly. shutdown the emp8130 enters sleep mode when the en pin is low. wh en this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandgap reference, are turned off, thus reducing the supply current to typically < 1ua. the low supply current makes the emp8 130 best suited for battery-powered applications. the maximum guaranteed voltage at the en pin to enter sleep mode is 0.4v. a minimum guaranteed voltage of 1.0v at the en pin will activate the emp8130. to constantly keep the regulator on, direct connection of the en pin to the vin pin is allowed.
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 10/12 package outline drawing sot-23-5 min. max. a 0.90 1.45 a1 0.00 0.15 b 0.30 0.50 c 0.08 0.25 d 2.70 3.10 e 1.40 1.80 e1 2.60 3.00 e l 0.30 0.60 0.95 bsc symbol dimension in mm
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 11/12 revision history revision date description 0.1 2014.02.11 initial version.
esmt preliminary emp8130 elite semiconductor memory technology inc. publication date : feb. 2014 revision : 0.1 12/12 important notice all rights reserved. no part of this document may be repr oduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docume nt are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is pr esented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express, implied or otherwise, is granted un der any patents, copyrights or other intellectual property righ ts of esmt or others. any semiconductor devices may have in herently a certain rate of failure. to minimize risks associated with cu stomer's application, adequate design and operating safeguards against inju ry, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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